Nonvolatile memory designs constantly strive to achieve a greater density of memory cells on a single chip. In order to increase cell density, much effort has been placed in reducing the size of the devices used to implement the memory array. Present-day designs are incorporating submicron memory cells (devices using less than one micrometer design rules) in order to achieve the higher density.
Ultimately, devices will become so small that further scaling is not possible. As the devices are scaled, other problems are encountered in metal interconnect layers and the gate oxide layers. While it is expected that devices will continue to be made smaller, the advances and chip density are not expected to be nearly as great as the density increase which has occurred over the last ten years.
Further, the state-of-the-art submicron devices suffer reliability problems. As each generation of scaled-down device emerges, it is expected that they too will suffer initial reliability problems.
Therefore, a need has arisen in the industry for a transistor structure which will increase the density of nonvolatile memory arrays using reliable design rules, presently in the range one to two micrometers.